Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage nodes (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
The source and drain select gates may be field-effect transistors having a fixed threshold voltage, i.e., a non-programmable threshold voltage. Due to variations in fabrication, such fixed threshold voltage field-effect transistors will often have varying threshold voltages for select gates coupled to the same control line. To address this variability, alternative configurations have replaced the fixed threshold voltage field-effect transistors of both the source and drain select gates with charge storage cells having charge storage nodes, e.g., similar to memory cells. For example, such source and drain select gates are sometimes referred to as programmable source and drain select gates. The threshold voltages of both charge storage cells acting as select gates are typically adjusted to a particular programmed state and are typically not erased during erase operations performed on the corresponding NAND string of memory cells.
In configurations using charge storage cells for the source and drain select gates, “dummy” word lines are typically located between the programmable select gates and the NAND string of memory cells to protect the threshold voltages programmed into respective source and drain select gates from being changed during erase operations performed on the corresponding NAND string of memory cells. This leads to added complexity and real estate to the memory array.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to (and, in some cases, formed by) a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
For some applications, flash memory stores a single bit per cell. For example, cells that store a single bit per cell are sometimes called single-level cells (SLCs). Each single-level cell is characterized by a specific threshold voltage, which is sometimes referred to as the Vt-level. Within each cell, two or more possible Vt-levels exist. These Vt-levels are controlled, for example, by the amount of charge that is programmed or stored on the charge storage nodes. For some NAND architectures, for example, a memory cell might have a Vt-level greater than zero in a programmed (e.g., logic zero) state and a Vt-level less than zero in an erase (e.g., logic one) state.
For other applications, flash memory may store multiple bits per cell. For example, cells that store multiple bits per cell are sometimes called multi-level cells (MLCs). For example, multi-level cells generally have different program Vt-level distributions, with each distribution corresponding to a distinct data state, thereby representing different data values or bit patterns.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to the select gates being used in existing memory arrays.